Hardware Simulation
Section 09: Hardware Certification (DO-254)
Definition
A verification method using computer-based models to evaluate the behavior of a hardware design against its requirements before physical implementation. For programmable logic, simulation typically involves functional simulation of HDL code, timing simulation with back-annotated delays, and system-level simulation of the integrated design.
Where This Shows Up
Simulation is a primary verification method for FPGA and ASIC designs under DO-254. Functional simulation verifies logical correctness using testbenches that exercise the design against its requirements. Timing simulation adds propagation delay information from synthesis and place-and-route to verify that the design meets timing requirements under worst-case conditions. Code coverage metrics (statement, branch, condition, expression, toggle) are used to assess the thoroughness of the simulation test suite, particularly at DAL A and B where structural coverage requirements apply.
Primary Sources
Section 6.1 — Verification Process, identifies simulation as a verification method for hardware design assurance.
Related Terms
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