DO-178C review
Multi-core processor evidence review for avionics suppliers
This page is for avionics suppliers, OEMs, Engineering teams when Multi-core processor selection for certified avionics puts multi-core processor evidence review on the critical path. EE checks interference channel analysis, WCET substantiation, processor configuration lock record against the approval basis, configuration baseline, effectivity, revision status, and source records named in the brief. The buyer receives a discrepancy register, evidence map, and closure request list for the next review gate. The work tests records and certification-data traceability only; it does not replace authority, delegate, approval-holder, or authorized-person decisions.
When this review is needed
- Use this review when Multi-core processor selection for certified avionics starts driving schedule or commercial exposure.
- An avionics architect putting a multi-core SoC in a certified box searching for what CAST-32A successors require.
- The highest-risk breakpoint is: interference channels inventoried from the datasheet while errata and undocumented arbitration are ignored, WCET measured on an idle system, and processor configuration left changeable after verification.
The problem
At this gate, what evidence a multi-core processor in avionics needs under AMC 20-193 and FAA equivalents, and whether the program's interference analysis will survive review. The file set covers the interference channel identification (shared cache, memory controllers, interconnects, I/O), configuration settings lockdown of the processor, WCET substantiation under contention, and the verification of mitigation means like partitioning of cores or bandwidth regulation. Known breakpoints include interference channels inventoried from the datasheet while errata and undocumented arbitration are ignored, WCET measured on an idle system, and processor configuration left changeable after verification.
What gets reviewed
- Review the buyer decision in the brief: Scope and review multi-core interference and WCET evidence against AMC 20-193 era expectations.
- Trace interference channel analysis to source date, revision, owner, and current configuration.
- Match effectivity for WCET substantiation to the serial range, article version, aircraft, or fleet in scope.
- At this gate, what evidence a multi-core processor in avionics needs under AMC 20-193 and FAA equivalents, and whether the program's interference analysis will survive.
Scope this review
Tell us the asset, the event, and the evidence in scope, and we will outline a focused first engagement.
Identify what is missing against the means of compliance.
What gets validated
- Record custody: interference channel analysis is checked for source, date, revision, and relationship to the current program.
- Coverage boundary: WCET substantiation must state where the evidence stops applying.
- Baseline comparison: installation, test, drawing, and compliance references are sampled for mismatched revisions.
- Disposition rule: unsupported assumptions are separated from acceptable limitations.
Evidence normally required
- Source record set for interference channel analysis
- Program file covering WCET substantiation
- Configuration baseline with approval basis and revision index
- Open issue log tied to processor configuration lock record
Common discrepancies
- The file set covers the interference channel identification (shared cache, memory controllers, interconnects, I/O), configuration settings lockdown of the processor, WCET.
- Known breakpoints include interference channels inventoried from the datasheet while errata and undocumented arbitration are ignored, WCET measured on an idle system, and processor.
- Revision mismatch leaves processor configuration lock record separated from the certificate, matrix, instruction, or delivered baseline.
- Storage completeness is higher than decision readiness because the file lacks a clear disposition for this buying stage.
What is at stake
Specific exposure for this page: interference channels inventoried from the datasheet while errata and undocumented arbitration are ignored, WCET measured on an idle system, and processor configuration left changeable after verification.
How the work runs
Frame Multi Core
Confirm the exact event, affected file set, buyer role, and decision standard before any interference channel analysis is treated as sufficient.
Trace Certification Support
Walk the named evidence from index entry to source artifact and mark where the trail supports, conflicts with, or fails to answer the page-specific question.
Sort Review Avionics
Group exceptions by closure route: document retrieval, data correction, engineering disposition, authority response, or contractual decision.
Package 178c Interference
Deliver the exception list, evidence map, and owner sequence in a form that can move directly into remediation, submittal cleanup, or transaction negotiation.
What the buyer receives
- Multi-core processor evidence review discrepancy register
- source map for interference channel analysis
- effectivity and configuration closure list
- decision summary with limits and escalation items
How the work fits into the transaction or program
What evidence a multi-core processor in avionics needs under AMC 20-193 and FAA equivalents, and whether the program's interference analysis will survive review. The evidence set centers on the interference channel identification (shared cache, memory controllers, interconnects, I/O), configuration settings lockdown of the processor, WCET substantiation under contention, and the verification of mitigation means like partitioning of cores or bandwidth regulation. The likely weak points are interference channels inventoried from the datasheet while errata and undocumented arbitration are ignored, WCET measured on an idle system, and processor configuration left changeable after verification. The output gives the software architect a cleanup register for Multi-core processor before multi-core processor selection for certified avionics.
Start with a single asset
Reduce finding cycles by checking the package first.
Regulatory limits
For multi-core processor evidence review, EE reviews interference channel analysis, WCET substantiation, processor configuration lock record for completeness, consistency, and traceability. The work does not issue approvals, approve data, grant relief, validate STCs, accept release certificates, or make airworthiness determinations. Final decisions remain with the responsible authority, delegate, approval holder, operator, or authorized person.
Specific to this review
- At this gate, what evidence a multi-core processor in avionics needs under AMC 20-193 and FAA equivalents, and whether the program's interference analysis.
- The file set covers the interference channel identification (shared cache, memory controllers, interconnects, I/O), configuration settings lockdown of the.
- Known breakpoints include interference channels inventoried from the datasheet while errata and undocumented arbitration are ignored, WCET measured on an idle.
- The scope uses the Multi Core Processor Certification question as the control point, so the review stays tied to Multi-core processor selection for certified avionics and the buyer decision behind it.
- The evidence starts with interference channel analysis and follows Support Evidence Review Avionics references until every exception has a source location and a reason code.
- The finding logic separates missing paperwork, conflicting status, stale revision data, and unsupported disposition because each class closes through a different owner.
- The timing matters for software architect: the output is useful only if the unresolved items are visible before acceptance, submittal, handback, or negotiation pressure fixes the sequence.
- The boundary control keeps Suppliers 178c Interference Channels questions in the records or certification lane and sends technical acceptance issues to the authorized people who own them.
- The handoff value comes from Multi-core processor evidence review discrepancy register; it gives the next reviewer a precise map instead of another broad request for a better file.
- The source discipline is stricter on this page than on a general audit because the claim being tested is Scope and review multi-core interference and WCET evidence against AMC 20-193 era expectations..
Sources
RTCA. Objectives and lifecycle data for airborne software assurance, by design assurance level (DAL A-E).
RTCA. Design assurance objectives and lifecycle data for airborne electronic hardware (FPGA/ASIC/PLD).
Frequently asked questions
What makes this standards review different from a general file audit?
The scope is tied to multi core processor certification and to the decision named in the request. A general audit can list weak records; this pass ranks the gaps by whether they block multi-core processor selection for certified avionics or can be closed later without changing the decision.
What evidence has to be available before this work starts?
The starting point is interference channel analysis, the current status source, and any index or matrix that tells reviewers where the supporting artifact should live. Missing inputs are logged as findings rather than filled with assumptions.
Who decides whether an open item is acceptable?
The review explains what the evidence supports and gives software architect a closure path. Acceptance remains with the buyer, operator, authority, delegated engineer, or authorized person responsible for the underlying airworthiness or certification decision.
Relevant glossary terms
Related pages
Where this fits
Talk to an engineer who has done this work
We will walk through your current state, the records or evidence involved, and a scoped first engagement.
Talk through the aircraft, records, evidence, deadline, and next useful step.